This invention relates, in general, to the testing of semiconductor wafers and, more particularly, to the mapping of faulty junctions in wafers by use of electron microscopes.
Semiconductor wafers may be constructed with many junctions, such as emitter-base and base collector junctions, which are used in the construction of electronic circuits on the wafers. The possibility of the presence of such faults lowers the yield in the production of semiconductor circuits. A low yield is of particular concern in very large scale integration VLSI semiconductor circuits due to the very large number of semiconductor junctions in the wafer. With increasing size and complexity of such wafers, the chance of a fault increases with a corresponding decrease in the likelihood of success in the manufacture of large circuits on a single wafer.
One technique of wafer examination employs an electron microscope in conjunction with the electrical energization of the electrical circuit on the wafer. The differences in potential across junctions and other points in the circuit are sufficient to alter the magnitude of secondary emission of electrons in response to the impingement of the electron beam. By moving the beam from point to point along the wafer circuit, differences in secondary emission occur. Reception of the secondary emission and recordation of the locations of the electron beam at each measurement of the emission provide an image of the wafer circuit. A description of the foregoing technique is provided in the magazine Electronics, July 14, 1981, at pages 105-112 in an article entitled "Scanning Electron Beam Probes VLSI Chips."
A second technique employs the electron microscope without the energization of an electrical circuit on the wafer to develop differing values of potential along the wafer. This technique is useful in providing pictorial presentations of the minute structures found in a transistor and other semiconductive devices. However, this technique suffers in that the information based on potential differences among circuit points is not available.
However, the combined use of circuit energization in conjunction with the electron microscope in the first technique cannot be employed in partially fabricated wafer circuits prior to the metallization step in the circuit fabrication process. This is because metal conducting paths are required to introduce the electronic potentials to the various points on the wafer. The foregoing limitation is a severe restriction on the use of the examination technique and introduces a problem in that adequate inspection of the wafer circuit cannot be accomplished part way through the fabrication process, particularly, before the metallization step.